FortifyIQ is seeking a Senior Hardware Design Engineer to lead complex ASIC and FPGA development initiatives. This senior-level role combines architectural definition, hands-on RTL implementation, and technical leadership to deliver high-performance, power-efficient silicon solutions. The position collaborates closely with firmware and verification teams to ensure reliable and scalable hardware designs throughout the full development lifecycle.
Responsibilities:
- Define hardware architecture and evaluate trade-offs for performance, area, and power efficiency
- Lead RTL development, integration, and verification across the design cycle
- Collaborate with firmware and verification teams to ensure high-quality silicon delivery
- Mentor junior engineers and conduct technical design reviews to promote best practices
- Provide design-in and silicon bring-up support for customer-facing projects
- Drive technical excellence through documentation, automation, and workflow optimization
Requirements:
- Strong proficiency in SystemVerilog for RTL design and digital architecture
- Experience with simulation tools such as Questa, Incisive, or VCS
- Proven expertise in ASIC or FPGA design, synthesis, and timing closure
- Scripting skills in Python, Perl, or Tcl for automation
- 10+ years of relevant hardware design experience
- BSEE or MSEE degree
Benefits:
- Flexible hybrid work environment
- Opportunity to lead high-impact silicon development projects
- Collaboration with cross-functional engineering teams
- Technical leadership and mentorship opportunities
Join FortifyIQ to architect and deliver next-generation silicon solutions in a dynamic engineering environment.