Verification Engineer

FortifyIQ is a semiconductor technology company focused on developing advanced chip and silicon solutions for high-performance applications. The Verification Engineer will support the validation of complex chip and subsystem designs by developing UVM-based environments, creating comprehensive test plans, and ensuring full functional and code coverage in collaboration with architecture and design teams.

FortifyIQ is seeking a Verification Engineer to contribute to the validation of advanced silicon and chip designs. This role focuses on developing robust verification environments, executing detailed test strategies, and collaborating with cross-functional engineering teams to ensure high-quality, high-performance products.

Responsibilities:
- Analyze chip and subsystem architecture to define verification requirements  
- Develop, maintain, and extend UVM-based verification environments  
- Create detailed test plans, test cases, and sequences for block- and chip-level validation  
- Debug functional design issues based on architectural specifications  
- Collaborate with design and architecture teams to meet quality and schedule objectives  
- Perform functional and code coverage analysis to ensure comprehensive validation  

Requirements:
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or related field  
- Proficiency in Verilog/SystemVerilog and UVM methodologies  
- Experience working in Linux environments and with industry-standard EDA tools  
- Strong understanding of verification methodologies and pre-silicon design flows  
- Excellent communication and teamwork skills  
- Experience with functional and code coverage closure  

Benefits:
- Opportunity to work on advanced high-performance silicon products  
- Collaborative engineering environment with cross-functional exposure  
- Involvement in full chip and subsystem validation efforts  
- Flexible remote work arrangement  

FortifyIQ provides a technically challenging environment where engineers contribute to ensuring design integrity and functional excellence across next-generation semiconductor platforms.