Principal Verification Engineer

FortifyIQ is a semiconductor technology company delivering advanced hardware solutions across multiple product lines. The Principal Verification Engineer will lead verification strategy and execution at both block and full-chip levels, ensuring functional accuracy, performance validation, and reliability through advanced UVM-based environments and cross-functional collaboration.

FortifyIQ is seeking a Principal Verification Engineer to lead verification initiatives across complex semiconductor product lines. This senior-level role is responsible for defining verification strategies, guiding methodology improvements, and ensuring full functional validation from block-level to full-chip designs.

Responsibilities:
- Lead verification planning and execution at both block and full-chip levels  
- Partner with architecture and design teams to align verification objectives with design intent  
- Develop, enhance, and maintain advanced UVM-based verification environments  
- Track and achieve coverage metrics to ensure complete functional validation  
- Collaborate with lab teams during silicon bring-up and debug activities  
- Drive verification methodology improvements and mentor junior engineers  

Requirements:
- MSEE with 10+ years or PhD with 7+ years of verification experience  
- Advanced expertise in SystemVerilog and UVM methodologies  
- Proficiency with EDA tools such as VCS, Xcelium, and IMC  
- Strong scripting and automation skills in Python or Perl  
- Excellent leadership, communication, and cross-functional collaboration skills  
- Deep understanding of pre-silicon verification flows and coverage closure  

Benefits:
- Opportunity to lead verification across multiple advanced product lines  
- Collaborative global engineering environment  
- Exposure to silicon bring-up and full-chip validation processes  
- Flexible remote work arrangement  

FortifyIQ offers a technically challenging environment where senior engineers shape verification strategies and ensure the highest standards of performance and reliability across semiconductor designs.